1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor integrated circuit, and more particularly, to a method and apparatus for manufacturing a fully-depleted (FD) silicon-on-insulator (SOI) CMOS device.
2. Description of the Related Art
Attention has recently been focused on silicon-on-insulator (SOI) technology from the viewpoint of improving transistor performance and efficiency. In the case of ordinary bulk CMOS, a transistor is formed on a silicon substrate. In the case of SOI CMOS, on the other hand, a transistor is formed on an SOI substrate having an insulator between the silicon substrate and a device region. Consequently, SOI CMOS have advantages such as lower power consumption due to reduction of parasitic capacitance and decreased leakage current as well as faster operation as a result of reduced junction capacitance in comparison with bulk CMOS.
A gate of SOI CMOS is formed on a silicon thin film formed on an insulator, and SOI CMOS is classified to two groups based on the thickness of the silicon thin film (referred to as an SOI layer). One group is a partially-depleted SOI (PD-SOI) and the other group is a fully-depleted SOI (FD-SOI). Normally, in the case of FD-SOI, the thickness of the SOI layer is about 50 nm or less when a design rule of about 0.2 μm is employed. If the thickness of the SOI layer is greater than 50 nm, the SOI CMOS becomes a PD-SOI due to the formation of a neutral region in the channel region of the transistor. An FD-SOI obtained by reducing the thickness of the SOI layer can reduce the gate voltage value (S value) in the subthreshold region as compared with PD-SOI, and has advantages (namely, faster operation and low current consumption) because of reduced off-leakage voltage and lowered Vt value (lower threshold voltage value).
If the thickness of the SOI layer is improper, the characteristics of FD-SOI are impaired. If the SOI layer is excessively thick, a PD-SOI results instead of an FD-SOI due to the formation of a neutral region in the channel region of the transistor. On the other hand, if the SOI layer is excessively thin and cobalt silicide (CoSi2) is formed in the source region and drain region composed of the SOI layer, it reacts with Si and Co in the channel and causes leakage.
Substrates for semiconductor integrated circuit production are often controlled and manufactured in production lot units. One example of a technology for controlling and manufacturing in production lot units is disclosed in Japanese Patent Application Kokai (Laid-open) No. H5-73578. This Japanese Patent Application describes a lot control device in which a single production lot is divided into a plurality of lot units, each lot is assigned an individual lot number at the time of that division, and the divided lots are rejoined to the single (original) production lot using the assigned lot numbers after having gone through some steps. Japanese Patent Application Kokai No. H4-239152 discloses a lot compilation method and device in which an optically-readable (scannable) identification code is imparted to the surface of each substrate in advance, the identification code of each substrate is scanned at the time of lot compilation, and lots are compiled based on the scanned identification codes.
Japanese Patent Application Kokai No. H7-302826 discloses a process for implanting impurities into a source and drain, measuring actual implantation depth and then altering gate length based on the measured implantation depth and a predetermined equation if the measured implantation depth is different from a desired depth.
Japanese Patent Application Kokai No. S63-249328 discloses technology relating to systemization of a semiconductor production line by inspecting semiconductor chips during the course of production, simulating operation and characteristics of an ultimate product (semiconductor device) using results obtained from the inspection and processing conditions of the next step, and then optimizing processing conditions of the next step for semiconductor chips currently being produced, based on the simulation results.
If there are variations in SOI layer thickness among a plurality of delivered SOI substrates, the technologies disclosed in Japanese Patent Applications Kokai No. H5-73578, No. H4-239152, No. H7-302826 and No. S63-249328 do not allow the production of FD-SOI of uniform quality.
In Japanese Patent Application Kokai No. H5-73578, SOI substrates are divided into a plurality of lot units irregardless of SOI layer thickness and lot numbers are assigned to the respective lots. Thus, there are variations in SOI layer thickness among the SOI substrates contained in each individual lot. Fixed process conditions are used for all substrates in a single lot. If semiconductor integrated circuits are manufactured in lot units, FD-SOI of uniform quality are unable to be produced.
In the lot compilation method and device disclosed in Japanese Patent Application Kokai No. H4-239152, lots are recompiled based on identification numbers imparted to the respective substrates in advance regardless of SOI layer thickness. Therefore, there are variations in SOI layer thickness among the SOI substrates contained within the same lot. If semiconductor integrated circuits are manufactured en bloc in such lot units containing a plurality of SOI substrates having variations in the SOI layer thickness, FD-SOI of uniform quality are unable to be produced.
In the example described in Japanese Patent Application Kokai No. H7-302826, actual implantation depth is inspected following implantation of impurities into a source and drain. In the manufacturing of FD-SOI, the source and drain are formed in an SOI layer. Therefore, if there are variations in SOI layer thickness among a plurality of SOI substrates, FD-SOI of uniform quality are unable to be produced.
In the production device disclosed in Japanese Patent Application Kokai No. S63-249328, processing conditions are decided for the next step based on processing results of a certain step. Since a plurality of SOI substrates are normally processed en bloc in each step of FD-SOI production, FD-SOI of uniform quality are unable to be produced if there are variations in SOI layer thickness among a plurality of SOI substrates. Deciding the processing conditions of the next step on the basis of processing results of a certain step does not solve the problem of unequal quality.